The present invention relates to a method of testing IC memories. More specifically, it relates to a method of testing memory cells such as random access memory (RAM) cells.
According to the conventional method of testing IC memories, the performance of unstable elements in the memory cells of the semiconductor device is presumed on the basis of maximum and minimum operation power-supply voltages. In the case of the RAM, the normal operation voltage is usually -5.2 volts with a permissible range of .+-.5%. Therefore, maximum and minimum operation limit voltages are applied to determine whether the contents of the IC memory are destroyed. When IC memories are tested by the above method, however, it becomes difficult to carry out testing by changing the voltage when peripheral circuits such as decoders, drivers, and output circuits become inoperative. With the above method, furthermore, it is difficult to determine the operation limit (data-holding limit) of the memory cells which are still operating at the operation voltage. Therefore, it is not possible to find cells which have a poor limit voltage for holding data, i.e., which make up a small margin of the cells in the cell array.